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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5531/32/33/34 16-bit and 24-bit adcs with ultra low noise pgia features l delta-sigma analog-to-digital converter linearity error: 0.0007% fs noise free resolution: up to 22.9-bits l chopper stabilized pgia (programmable gain instrumentation amplifier) 6 nv/ ? hz @ 0.1 hz 100 pa input current with gains >1 l scalable input span: 5 mv to 85 mv 80 mv to 1.2 v 200 mv to 2.5 v l two or four channel differential mux l scalable v ref input: +1.0 v to +5.0 v l simple three-wire serial interface spi? and microwire? compatible schmitt trigger on serial clock (sclk) l r/w calibration registers per channel l selectable word rates: 7.5 hz to 3,840 hz l power supply configurations va+ = +5 v; va- = 0 v; vd+ = +3 v to +5 v va+ = +2.5 v; va- = -2.5 v; vd+ = +3 v to +5 v va+ = +3 v; va- = -3 v; vd+ = +3 v general description the cs5531/32/33/34 are highly integrated ds analog- to-digital converters (adcs) which use charge-balance techniques to achieve 16-bit (cs5531/33) and 24-bit (cs5532/34) performance. the adcs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications. to accommodate these applications, the adcs come as either two-channel (cs5531/32) or four-channel (cs5533/34) devices and include a very low noise chop- per-stabilized instrumentation amplifier (6 nv/ ? hz @ 0.1 hz) with selectable gains of 1, 2, 4, 8, 16, and 32. these adcs also include a fourth order ds modulator followed by a digital filter which provides ten selectable output word rates of 7.5 hz, 15 hz, 30 hz, 60 hz, 120 hz, 240 hz, 480 hz, 960 hz, 1.92 khz, and 3.84 khz (xin = 4.9152 mhz). to ease communication between the adcs and a micro- controller, the converters include a simple three-wire se- rial interface which is spi? and microwire? compatible with a schmitt trigger input on the serial clock (sclk). high dynamic range, programmable output rates, and flex- ible power supply options makes these adcs ideal solutions for weigh scale and process control applications. ordering information see page 37 va+ c1 c2 vref+ vref- vd+ differential 4 th order ds modulator pgia 1,2,4,8, programmable sinc fir filter mux (cs5533/34 shown) ain1+ ain1- ain2+ ain2- ain3+ ain3- ain4+ ain4- serial interface latch clock generator calibration sram/control logic dgnd cs sdi sdo sclk xout xin a1 a0 va- 16,32 jan 99 ds289pp1
cs5531/32/33/34 2 ds289pp1 table of contents characteristics/specifications ............................................................ 4 analog characteristics................................................................... 4 rms noise................................................................................................. 5 noise free resolution (bits) ........................................................... 5 5 v digital characteristics ............................................................. 6 3 v digital characteristics ............................................................. 6 dynamic characteristics ................................................................. 6 absolute maximum ratings .............................................................. 7 switching characteristics ............................................................. 8 general description ................................................................................ 10 analog input ............................................................................................. 10 analog input span ..................................................................................11 multiplexed settling limitations .......................................................... 11 serial port ................................................................................................. 11 system initialization ........................................................................... 11 command register quick reference .............................................. 13 command register descriptions ....................................................... 14 serial port interface ........................................................................... 18 reading/writing on-chip registers ................................................... 19 setting up the csrs for a measurement ........................................... 19 channel-setup register descriptions ............................................... 20 configuration register .............................................................................. 21 power consumption ........................................................................... 21 reset system ..................................................................................... 22 input short .......................................................................................... 22 guard signal ...................................................................................... 22 voltage reference select .................................................................. 22 output latch pins ............................................................................... 23 configuration register descriptions ................................................... 24 calibration ................................................................................................. 25 calibration registers .......................................................................... 25 gain register .................................................................................... 25 offset register .................................................................................. 25 performing calibrations ...................................................................... 26 self calibration ................................................................................... 26 system calibration ............................................................................. 26 calibration tips .................................................................................. 27 limitations in calibration range ........................................................ 27 performing conversions ........................................................................... 28 single conversion mode (mc = 0) ..................................................... 28 multiple conversions mode (mc = 1) ................................................. 28 use of pointers in command byte ..................................................... 28 spi? is a trademark of motorola inc., microwire? is a trademark of national semiconductor corp. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product information describes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. however, the information is subject to chan ge without notice and is provided as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. f or the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, trademarks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval sys- tem, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names o f products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respec tive owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http:/ /www.cirrus.com.
cs5531/32/33/34 ds289pp1 3 conversion output coding ....................................................................... 29 conversion data register descriptions ............................................. 30 output coding .................................................................................... 31 digital filter .............................................................................................. 31 clock generator ....................................................................................... 31 power supply arrangements .................................................................... 32 getting started ......................................................................................... 32 pcb layout .............................................................................................. 34 pin descriptions ........................................................................................ 35 clock generator ....................................................................................... 35 control pins and serial data i/o .............................................................. 35 measurement and reference inputs ........................................................ 36 power supply connections ...................................................................... 36 specification definitions ........................................................................ 37 ordering guide ........................................................................................... 37 package drawings .................................................................................... 38 table of figures sdi write timing (not to scale) ........................................................................... 9 sdo read timing (not to scale) ......................................................................... 9 multiplexer configuration. .................................................................................. 10 input models for ain+ and ain- pins. ................................................................ 11 cs5531/32/33/34 register diagram. ................................................................. 12 command and data word timing. ..................................................................... 18 guard signal shielding scheme. ....................................................................... 22 input reference model when vrs = 1. .............................................................. 22 input reference model when vrs = 0. .............................................................. 22 self calibration of offset. ................................................................................... 26 self calibration of gain. ..................................................................................... 26 system calibration of offset. ............................................................................. 27 system calibration of gain. ............................................................................... 27 digital filter response (word rate = 60 hz). .................................................... 31 cs5532 configured with a single +5 v supply. ................................................. 32 cs5532 configured with 2.5 v analog supplies. ............................................. 33 cs5532 configured with 3 v analog supplies. ................................................ 33 bridge with series resistors. ............................................................................. 34
cs5531/32/33/34 4 ds289pp1 characteristics/specifications analog characteristics (t a = 25 c; va+, vd+ = 5 v 5%; vref+ = 5 v, va-, vref- = agnd, fclk = 4.9125 mhz, owr (output word rate) = 60 hz, bipolar mode, gain = 32; see notes 1 and 2.) notes: 1. applies after system calibration at any temperature within -40 c ~ +85 c. 2. specifications guaranteed by design, characterization, and/or test. 3. specification applies to the device only and does not include any effects by external parasitic thermocouples. 4. drift over specified temperature range after calibration at power-up at 25 c. 5. see the section of the data sheet which discusses input models. parameter cs5531/33 cs5532/34 unit min typ max min typ max accuracy linearity error - 0.0015 0.003 - 0.0007 0.0015 %fs no missing codes 16 - - 24 - - bits bipolar offset (note 3) - 12 - 16 32 lsb 24 unipolar offset (note 3) - 2 4- 32 64 lsb 24 offset drift (notes 3 and 4) - 20 - - 20 - nv/c offset drift /1000 hours. - tbd - - tbd - ppm bipolar full scale error - 8 31 - 8 31 ppm unipolar full scale error - 16 62 - 16 62 ppm full scale drift (note 4) - 1 3 - 1 3 ppm/c full scale drift /1000 hours. - tbd - - tbd - ppm parameter min typ max unit voltage reference input range (vref+) - (vref-) 1 2.5 va+ v common mode rejection dc 50, 60 hz - - 120 120 - - db db input capacitance 11 - 22 pf cvf current (note 5) - 100 - na analog input common mode + signal on ain+ or ain- bipolar/unipolar mode gain = 1 gain = 2, 4, 8, 16, 32 va- va- + 0.7 - - va+ va+ - 1.7 v v common mode rejection dc 50, 60 hz - - 120 120 - - db db input capacitance - 60 - pf cvf current on ain+ or ain- gain = 1 (note 5) gain = 2, 4, 8, 16, 32 - - 100 100 - - na pa open circuit detect current 100 300 - na system calibration specifications full scale calibration range bipolar/unipolar mode - tbd - %fs offset calibration range bipolar/unipolar mode - tbd - %fs
cs5531/32/33/34 ds289pp1 5 analog characteristics (continued) (see notes 1 and 2.) notes: 6. all outputs unloaded. all input cmos levels. rms noise (notes 7 and 8) notes: 7. wideband noise aliased into the baseband. referred to the input. typical values shown for 25 c. 8. for peak-to-peak noise multiply by 6.6 for all ranges and output rates. noise free resolution (bits) = log (vin p-p /(6.6xrms noise))/log(2) specifications are subject to change without notice. parameter min typ max unit power supplies dc power supply currents (normal mode) i a+ i d+ - - tbd tbd 6.5 1.5 ma ma power consumption normal mode (note 6) standby sleep - - - tbd tbd tbd 40 - - mw mw w power supply rejection dc positive supplies dc negative supply - - 120 120 - - db db output rate (hz) -3 db filter frequency instrumentation amplifier gain x32x16x8x4x2x1 7.5 1.94 8.9nv 10.4nv 14.9nv 26.0nv 49.8nv 98.6nv 15 3.88 12.6nv 14.6nv 20.9nv 36.6nv 70.2nv 138.9nv 30 7.75 17.8nv 20.7nv 29.6nv 51.6nv 99.1nv 196.0nv 60 15.5 25.1nv 29.2nv 41.8nv 72.9nv 139.9nv 276.8nv 120 31 35.6nv 41.4nv 59.1nv 103.1nv 197.9nv 391.5nv 240 62 136.3nv 260.0nv 513.5nv 1023.6nv 2045.6nv 4090.4nv 480 122 193.6nv 369.2nv 729.3nv 1453.9nv 2905.6nv 5810.0nv 960 230 273.7nv 522.7nv 1032.6nv 2058.9nv 4114.5nv 8227.4nv 1,920 390 469.6nv 912.3nv 1811.0nv 3615.1nv 7226.9nv 14452.0nv 3,840 780 2693.4nv 5378.9nv 10754.0nv 21505.9nv 43010.9nv 86021.3nv output rate (hz) -3 db filter frequency instrumentation amplifier gain x32 x16 x8 x4 x2 x1 7.5 1.94 21.4 22.2 22.6 22.8 22.9 22.9 15 3.88 20.9 21.7 22.1 22.3 22.4 22.4 30 7.75 20.4 21.2 21.6 21.8 21.9 21.9 60 15.5 19.9 20.7 21.1 21.3 21.4 21.4 120 31 19.4 20.2 20.6 20.8 20.9 20.9 240 62 17.4 17.5 17.5 17.5 17.5 17.5 480 122 16.9 17.0 17.0 17.0 17.0 17.0 960 230 16.4 16.5 16.5 16.5 16.5 16.5 1,920 390 15.7 15.7 15.7 15.7 15.7 15.7 3,840 780 13.1 13.1 13.1 13.1 13.1 13.1
cs5531/32/33/34 6 ds289pp1 5 v digital characteristics (t a = 25 c; va+, vd+ = 5 v 5%; va-, gnd = 0; see notes 2 and 9.) notes: 9. all measurements performed under static conditions. 3 v digital characteristics (t a = 25 c; va+ = 5v 5%; vd+ = 3.0v10%; va-,gnd = 0; see notes 2 and 9.) dynamic characteristics parameter symbol min typ max unit high-level input voltage v ih 0.6 vd+ - vd+ v low-level input voltage v il 0.0 - 0.8 v high-level output voltage i out = -5.0 ma v oh (vd+) - 1.0 - - v low-level output voltage i out = 5.0 ma v ol --0.4v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf parameter symbol min typ max unit high-level input voltage v ih 0.6 vd+ - vd+ v low-level input voltage v il 0.0 - 0.8 v high-level output voltage i out = -5.0 ma v oh (vd+) - 1.0 - - v low-level output voltage i out = 5.0 ma v ol --0.4v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf parameter symbol ratio unit modulator sampling frequency f s xin/16 hz filter settling time to 1/2 lsb (full scale step) t s xin/16 s
cs5531/32/33/34 ds289pp1 7 absolute maximum ratings (agnd, dgnd = 0 v; see note 10.) notes: 10. all voltages with respect to ground. 11. va+ and va- must satisfy {(va+) - (va-)} +6.6 v. 12. vd+ and va- must satisfy {(vd+) - (va-)} +7.5 v. 13. applies to all pins including continuous overvoltage conditions at the analog input (ain) pins. 14. transient current of up to 100 ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. 15. total power dissipation, including all input currents and output currents. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max unit dc power supplies (notes 11 and 12) positive digital positive analog negative analog vd+ va+ va- -0.3 -0.3 +0.3 - - - +6.0 +6.0 -6.0 v v v input current, any pin except supplies (notes 13 and 14) i in --10ma output current i out --25ma power dissipation (note 15) pdn - - 500 mw analog input voltage vref pins ain pins v inr v ina 0.3 0.3 - - (va+) + 0.3 (va+) + 0.3 v v digital input voltage v ind -0.3 - (vd+) + 0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c
cs5531/32/33/34 8 ds289pp1 switching characteristics (t a = 25 c; va+ = 2.5v or 5v 5%; va- = -2.5v5% or agnd; vd+ = 3.0 v 10% or 5 v 5%; levels: logic 0 = 0 v, logic 1 = vd+; c l = 50 pf.)) notes: 16. device parameters are specified with a 4.9125 mhz clock. 17. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. 18. oscillator start-up time varies with crystal parameters. this specification does not apply when using an external clock source. parameter symbol min typ max unit master clock frequency (note 16) external clock or internal oscillator xin 14.91525 mhz master clock duty cycle 40 - 60 % rise times (note 17) any digital input except sclk sclk any digital output t rise - - - - - 50 1.0 100 - s s ns fall times (note 17) any digital input except sclk sclk any digital output t fall - - - - - 50 1.0 100 - s s ns start-up oscillator start-up time xtal = 4.9152mhz (note 18) t ost -20-ms serial port timing serial clock frequency sclk 0 - 2 mhz serial clock pulse width high pulse width low t 1 t 2 250 250 - - - - ns ns sdi write timing cs enable to valid latch clock t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sclk falling prior to cs disable t 6 100 - - ns sdo read timing cs to data valid t 7 --150ns sclk falling to new data bit t 8 --150ns cs rising to sdo hi-z t 9 --150ns
cs5531/32/33/34 ds289pp1 9 cs sclk msb msb-1 lsb sdi t3 t6 t4 t5 t1 t2 sdi write timing (not to scale) cs sclk msb msb-1 lsb sdo t7 t9 t8 t1 t2 sdo read timing (not to scale)
cs5531/32/33/34 10 ds289pp1 general description the cs5531/32/33/34 are highly integrated ds an- alog-to-digital converters (adcs) which use charge-balance techniques to achieve 16-bit (cs5531/33) and 24-bit (cs5532/34) performance. the adcs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications. to accommodate these applications, the adcs come as either two-channel (cs5531/32) or four- channel (cs5533/34) devices and include a very low noise chopper-stabilized programmable gain instrumentation amplifier (pgia, 6 nv/ ? hz @ 0.1 hz) with selectable gains of 1, 2, 4, 8, 16, and 32. these adcs also include a fourth order ds modulator followed by a digital filter which pro- vides ten selectable output word rates of 7.5 hz, 15 hz, 30 hz, 60 hz, 120 hz, 240 hz, 480 hz, 960 hz, 1.92 khz, and 3.84 khz (xin = 4.9152 mhz). to ease communication between the adcs and a micro-controller, the converters include a simple three-wire serial interface which is spi? and mi- crowire? compatible with a schmitt trigger input on the serial clock (sclk). analog input figure 1 illustrates a block diagram of the cs5531/32/33/34. the front end consists of a multi- plexer, a unity gain coarse/fine charge input buffer, and a programmable gain chopper-stabilized instru- mentation amplifier. the unity gain buffer is activat- ed any time conversions are performed with a gain of one and the instrumentation amplifier is activated any time conversions are performed with gain set- tings greater than one. the unity gain buffer is designed to accommodate rail to rail input signals. the common-mode plus signal range for the unity gain buffer amplifier is va- to va+. typical cvf (sampling) current for the unity gain buffer amplifier is about 10 na (xin = 4.9152 mhz, see figure 2). the instrumentation amplifier is chopper-stabi- lized and operates with a chop clock frequency of xin/128. the cvf (sampling) current into the in- strumentation amplifier is less than 300 pa over -40c to +85c. the common-mode plus signal range of the instrumentation amplifier is (va-) + 0.7 v to (va+) - 1.7 v. vref+ sinc digital filter xgain m u x ain2+ ain2- ain1+ ain1- cs5531/32 in+ in- ain4+ ain4- * * * ain1+ ain1- cs5533/34 m u x in+ in- in+ in- gain is the gain setting of the pgia (i.e. 2, 4, 8, 16, 32) x1 x1 x1 vref- x1 differential 4 order ds modulator th 5 programmable sinc digital filter 3 serial port 1000 w 1000 w 22 nf c1 pin c2 pin figure 1. multiplexer configuration.
cs5531/32/33/34 ds289pp1 11 figure 2 illustrates the input models for the ampli- fiers. the dynamic input current for each of the pins can be determined from the models shown. note: the c=2.5pf and c = 16pf capacitors are for input current modeling only. for physical input capacitance see input capacitance specification under analog characteristics . analog input span the full scale input signal that the converter can dig- itize is a function of the gain setting and the refer- ence voltage connected between the vref+ and vref- pins. the full scale of the converter is ((vref+) - (vref-))/(gxa), where g is the gain of the amplifier and a is 2 for vrs = 0 or a is 1 for vrs = 1. after reset, the unity gain buffer is en- gaged. with a 2.5v reference this would make the full scale input range default to 2.5 v. by activating the instrumentation amplifier (i.e. a gain setting oth- er than 1) and using a gain setting of 32, the full scale input range can quickly be set to 2.5/32 or about 78mv. note that these input ranges assume the cali- bration registers are set to their default values (i.e. gain = 1.0 and offset = 0.0). multiplexed settling limitations the settling performance of the cs5531/32/33/34 in multiplexed applications is affected by the sin- gle-pole low-pass filter which follows the instru- mentation amplifier (see figure 1). to achieve data sheet settling and linearity specifications, it is rec- ommended that a 22 nf c0g capacitor be used. ca- pacitors as low as 10 nf can be used with some noise degradation. serial port the cs5531/32/33/34 have a serial port which is used to transfer information between a micro-con- troller and the adc. the serial port is managed by an on-chip controller. the on-chip controller con- tains a command register, four channel-setup regis- ters (csrs), a configuration register, a conversion data register (read only), and a gain and offset reg- ister for each input channel. all registers, except the 8-bit command register, are 32-bits in length. figure 3 depicts a block diagram of the on-chip controllers internal registers. system initialization the cs5531/32/33/34 provide no power-on-reset function. to initialize the adcs, the user must per- form a software reset by resetting the adcs serial port with the serial port initialization sequence. this sequence resets the serial port to the command mode and is accomplished by transmitting 15 sync1 command bytes (0xff hexadecimal), fol- lowed by one sync0 command (0xfe hexadeci- mal). the sequence can be initiated at anytime to reinitialize the serial port. to complete the system initialization sequence, the user must also perform a system reset by setting the reset system (rs) bit in the configuration register. a system reset can also be initiated at any time by writing a logic 1 to the rs bit in the configuration register. after a sys- tem reset cycle is complete, the rs bit is automati- ain gain = 2, 4, 8, 16, 32 c = 2.5 pf f = gain = 1 ain c = 16 pf f coarse 1 f fine 1 v 20 mv i = fv c os os n v 1 mv i = fv c os os n xin 128 f = xin 16 figure 2. input models for ain+ and ain- pins.
cs5531/32/33/34 12 ds289pp1 cally returned to logic 0, and the on-chip registers are initialized to the following states: after a system initialization or reset, the on-chip controller is initialized into command mode where it waits for a valid command (the first 8-bits trans- mitted into the serial port are transmitted into the command register). once a valid command is re- ceived and decoded, the byte instructs the converter to either acquire data from or transfer data to an in- ternal register(s), or perform a conversion or a cal- ibration. the command register descriptions section can be used to decode all valid commands. offset 1 (1 x 32) offset 2 (1 x 32) offset 3 (1 x 32) offset 4 (1 x 32) gain 1 (1 x 32) gain 2 (1 x 32) gain 3 (1 x 32) gain 4 (1 x 32) setup 1 (1 x 16) setup 2 (1 x 16) setup 4 (1 x 16) setup 6 (1 x 16) setup 8 (1 x 16) setup 3 (1 x 16) setup 5 (1 x 16) setup 7 (1 x 16) offset registers (4 x 32) gain registers (4 x 32) channel setup registers (4 x 32) conversion data register (1 x 32) configuration register (1 x 32) power save select low power mode reset system input short guard signal voltage reference select output latch channel select gain word rate unipolar/bipolar output latch delay time output latch select open circuit detect cs sdi sdo sclk cs5533/34 only read only command register (1 8) write only serial interface data (1 x 32) figure 3. cs5531/32/33/34 register diagram. configuration register: 00000000(h) offset registers: 00000000(h) gain registers: 08000000(h) channel setup registers: 00000000(h)
cs5531/32/33/34 ds289pp1 13 command register quick reference d7(msb)d6d5d4d3d2d1d0 0 ara cs1 cs0 r/w rsb2 rsb1 rsb0 bit name value function d7 command bit, c 0 1 must be logic 0 for these commands. these commands are invalid if this bit is logic 1. d6 access registers as arrays, ara 0 1 ignore this function. access the respective registers, offset, gain, or channel-setup, as an array of regis- ters. the particular registers accessed are determined by the rs bits. the registers are accessed msb first with physical channel 0 accessed first followed by physical channel 1 next and so forth. d5-d4 channel select bits, cs1-cs0 00 01 10 11 cs1-cs0 provide the address of one of the two (four for cs5533/34) physical input channels. these bits are also used to access the calibration registers associated with the respective physical input channel. note that these bits are ignored when reading data register. d3 read/write , r/w 0 1 write to selected register. read from selected register. d2-d0 register select bit, rsb3-rsb0 000 001 010 011 100 101 110 111 reserved offset register gain register configuration register conversion data register channel-setup registers reserved reserved d7(msb)d6d5d4d3d2d1d0 1 mc csrp2 csrp1 csrp0 cc2 cc1 cc0 bit name value function d7 command bit, c 0 1 these commands are invalid if this bit is logic 0. must be logic 1 for these commands. d6 multiple conver- sions, mc 0 1 perform fully settled single conversions. perform conversions continuously. d5-d3 channel-setup reg- ister pointer bits, csrp 000 ... 111 these bits are used as pointers to the channel-setup registers. either a single con- version or continuous conversions are performed on the channel setup register pointed to by these bits. d2-d0 conversion/calibra- tion bits, cc2-cc0 000 001 010 011 100 101 110 111 normal conversion self-offset calibration self-gain calibration reserved reserved system-offset calibration system-gain calibration reserved
cs5531/32/33/34 14 ds289pp1 command register descriptions read/write all offset calibration registers function: these commands are used to access the offset registers as arrays. r/w (read/write) 0 write to selected register. 1 read from selected register. read/write all gain calibration registers function: these commands are used to access the gain registers as arrays. r/w (read/write) 0 write to selected register. 1 read from selected register. read/write all channel-setup registers function: these commands are used to access the channel-setup registers as arrays. r/w (read/write) 0 write to selected register. 1 read from selected register. read/write individual offset register function : these commands are used to access each offset register separately. cs1 - cs0 decode the registers accessed. r/w (read/write) 0 write to selected register. 1 read from selected register. cs[1:0] (channel select bits) 00 offset register 1 01 offset register 2 10 offset register 3 11 offset register 4 d7(msb)d6d5d4d3d2d1d0 0100r/w 001 d7(msb)d6d5d4d3d2d1d0 0100r/w 010 d7(msb)d6d5d4d3d2d1d0 0100r/w 101 d7(msb)d6d5d4d3d2d1d0 0 0 cs1 cs0 r/w 001
cs5531/32/33/34 ds289pp1 15 read/write individual gain register function : these commands are used to access each gain register separately. cs1 - cs0 decode the reg- isters accessed. r/w (read/write) 0 write to selected register. 1 read from selected register. cs[1:0] (channel select bits) 00 gain register 1 01 gain register 2 10 gain register 3 11 gain register 4 read/write individual channel-setup register function : these commands are used to access each channel-setup register separately. cs1 - cs0 de- code the registers accessed. r/w (read/write) 0 write to selected register. 1 read from selected register. cs[1:0] (channel select bits) 00 channel-setup register 1 01 channel-setup register 2 10 channel-setup register 3 11 channel-setup register 4 read/write configuration register function: these commands are used to read from or write to the configuration register. r/w (read/write) 0 write to selected register. 1 read from selected register. d7(msb)d6d5d4d3d2d1d0 0 0 cs1 cs0 r/w 010 d7(msb)d6d5d4d3d2d1d0 0 0 cs1 cs0 r/w 101 d7(msb)d6d5d4d3d2d1d0 0000r/w 011
cs5531/32/33/34 16 ds289pp1 perform conversion function: these commands instruct the adc to perform either a single conversion or continuous conver- sions on the physical input channel pointed to by the pointer bits (csrp2 - crsp0). mc (multiple conversions) 0 perform fully settled single conversions. 1 perform conversions continuously. csrp [2:0] (channel setup register pointer bits) 000 setup 1 001 setup 2 010 setup 3 011 setup 4 100 setup 5 101 setup 6 110 setup 7 111 setup 8 read conversion data register function: this command is used to read from the conversion data register. d7(msb)d6d5d4d3d2d1d0 1 mc csrp2 csrp1 csrp0 0 0 0 d7(msb)d6d5d4d3d2d1d0 00001100
cs5531/32/33/34 ds289pp1 17 perform calibration function: these commands instruct the adc to perform a calibration on the physical input channel se- lected by the setup register which is chosen by the command byte pointer bits (csrp2 - crsp0). csrp [2:0] (channel setup register pointer bits) 000 setup 1 001 setup 2 010 setup 3 011 setup 4 100 setup 5 101 setup 6 110 setup 7 111 setup 8 cc [2:0] (calibration control bits) 000 reserved 001 self-offset calibration 010 self-gain calibration 011 reserved 100 reserved 101 system-offset calibration 110 system-gain calibration 111 reserved sync1 function: part of the serial port re-initialization sequence. sync0 function: end of the serial port re-initialization sequence. null function: this command is used to clear a port flag and keep the converter in the continuous conversion mode. d7(msb)d6d5d4d3d2d1d0 1 0 csrp2 csrp1 csrp0 cc2 cc1 cc0 d7(msb)d6d5d4d3d2d1d0 11111111 d7(msb)d6d5d4d3d2d1d0 11111110 d7(msb)d6d5d4d3d2d1d0 00000000
cs5531/32/33/34 18 ds289pp1 serial port interface the cs5531/32/33/34s serial interface consists of four control lines: cs , sdi, sdo, sclk. figure 4 details the command and data word timing. cs , chip select, is the control line which enables access to the serial port. if the cs pin is tied low, the port can function as a three wire interface. sdi, serial data in, is the data signal used to trans- fer data to the converters. sdo, serial data out, is the data signal used to transfer output data from the converters. the sdo output will be held at high impedance any time cs is at logic 1. figure 4 illustrates the serial sequence necessary to write to, or read from the serial ports registers. sclk, serial clock, is the serial bit-clock which controls the shifting of data to or from the adcs serial port. the cs pin must be held low (logic 0) before sclk transitions can be recognized by the port logic. to accommodate optoisolators sclk is designed with a schmitt-trigger input to allow an optoisolator with slower rise and fall times to di- rectly drive the pin. additionally, sdo is capable of sinking or sourcing up to 5 ma to directly drive an optoisolator led. sdo will have less than a 400 mv loss in the drive voltage when sinking or sourc- ing 5 ma. command time 8 sclks data time 32 sclks write cycle cs sclk sdi msb command time 8 sclks cs sclk sdi read cycle sdo msb lsb command time 8 sclks 8 sclks clear sdo flag sdo sclk sdi msb lsb * td = xin/owr clock cycles for each conversion except the first conversion which will take xin/owr + 7 clock cycles xin/owr clock cycles t * d cs data time 32 sclks data time 32 sclks lsb data conversion cycle figure 4. command and data word timing.
cs5531/32/33/34 ds289pp1 19 reading/writing on-chip registers the cs5531/32/33/34s offset, gain, configuration, and channel-setup registers are readable and writ- able while the conversion data register is read only. as shown in figure 4, to write to a particular regis- ter the user must transmit the appropriate write command and then follow that command by 32 bits of data. for example, to write 0x80000000 (hexa- decimal) to physical channel ones gain register, the user would first transmit the command byte 0x02 (hexadecimal) followed by the data 0x80000000 (hexadecimal). similarly, to read a particular register the user must transmit the appro- priate read command and then acquire the 32 bits of data. once a register is written to or read from, the serial port returns to the command mode. in addition to accessing the internal registers one at a time, the gain and offset registers as well as the channel-setup registers, can be accessed as arrays (i.e. the entire register set can be accessed with one command). for example, to write 0x80000000 (hexadecimal) to all four gain registers, the user would transmit the command 0x42 (hexadecimal) followed by four iterations of 0x80000000 (hexa- decimal), (i.e. 0x42 followed by 0x80000000, 0x80000000, 0x80000000, 0x80000000). the reg- isters are written to or read from in sequential order (i.e, 1, followed by 2, then 3, then 4). once the reg- isters are written to or read from, the serial port re- turns to the command mode. setting up the csrs for a measurement the cs5531/32/33/34 have four channel-setup registers (csrs). each csr contains two 16-bit setups which are programmed by the user to contain data conversion information such as: 1) which phys- ical channel will be converted, 2) at what gain will the channel be converted, 3) at what word rate will the channel be converted, 4) will the output conver- sion be unipolar or bipolar, 5) what will be the state of the output latch during the conversion, 6) will the converter delay the start of a conversion to allow time for the output latch to settle before the conver- sion is begun, and 7) will the open circuit detect cur- rent source be activated for that setup. note that a particular physical input channel can be represent- ed in more than one setup with different output rates, gain ranges, etc. (i.e. each setup is indepen- dently defined). each 32-bit csr is individually accessible and contains two 16-bit setups. as an example, to con- figure setup 1 in the cs5531/32/33/34 with the write individual channel-setup register command (0x05 hexadecimal), bits 31 to 16 of csr 1 con- tains the information for setup 1 and bits 15 to 0 contain the information for setup 2. note that while reading/writing csrs, two setups are accessed in pairs as a single 32-bit csr register. even if one of the setups isnt used, it must be written to or read. examples detailing the power of the csrs are pro- vided in the use of pointers in the command byte section.
cs5531/32/33/34 20 ds289pp1 channel-setup register descriptions cs1-cs0 (channel select bits) [31:30] [15:14] 00 select physical channel 1. 01 select physical channel 2. 10 select physical channel 3. 11 select physical channel 4. g2-g0 (gain bits) [29:27] [13:11] 000 gain = 1, (input span = [(vref+)-(vref-)]/1 for unipolar). 001 gain = 2, (input span = [(vref+)-(vref-)]/2 for unipolar). 010 gain = 4, (input span = [(vref+)-(vref-)]/4 for unipolar). 011 gain = 8, (input span = [(vref+)-(vref-)]/8 for unipolar). 100 gain = 16, (input span = [(vref+)-(vref-)]/16 for unipolar). 101 gain = 32, (input span = [(vref+)-(vref-)]/32 for unipolar). wr3-wr0 (word rate) [26:23] [20:7] word rates apply to continuous conversion mode. in single conversion mode, an output will take three conversions to settle. only the third output will be provided to the serial port. bit wr (4.9152 mhz) wr (4.096 mhz) clock cycles 0000 120 hz 100 hz (40960 xin cycles) 0001 60 hz 50 hz (81920 xin cycles) 0010 30 hz 25 hz (163840 xin cycles) 0011 15 hz 12.5 hz (327680 xin cycles) 0100 7.5 hz 6.25 hz (655360 xin cycles) 1000 3840 hz 3200 hz (1280 xin cycles) 1001 1920 hz 1600 hz (2560 xin cycles) 1010 960 hz 800 hz (5120 xin cycles) 1011 480 hz 400 hz (10240 xin cycles) 1100 240 hz 200 hz (20480 xin cycles) all other combinations are not used. d31(msb) d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 cs1 cs0 g2 g1 g0 wr3 wr2 wr1 wr0 u/b ol1 ol0 dt ocd nu nu d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cs1 cs0 g2 g1 g0 wr3 wr2 wr1 wr0 u/b ol1 ol0 dt ocd nu nu csr #1 setup 1 bits <127:112> setup 2 bits <111:96> #4 setup 7 bits <31:16> setup 8 bits <15:0>
cs5531/32/33/34 ds289pp1 21 u/b (unipolar / bipolar) [22] [6] 0 select bipolar mode. 1 select unipolar mode. ol1-ol0 (output latch bits) [21:20] [5:4] the latch bits will be set to the logic state of these bits upon command word execution when the logic select bit (ls) in the configuration register is logic 0. note that the logic outputs on the chip are powered from va+ and va-. 00 a0 = 0, a1 = 0 01 a0 = 0, a1 = 1 10 a0 = 1, a1 = 0 11 a0 = 1, a1 = 1 dt (delay time bit) [19] [3] when set, the converter will wait for a delay time before starting a conversion. this allows settling time for a0 and a1outputs before a conversion begins. the delay time will be 1280 xin cycles. 0 normal mode. 1 wait 1280 xin cycles before starting conversion. ocd (open circuit detect bit) [18] [2] when set, this bit activates a 300 na current source on the input channel (ain+) selected by the channel select bits. note that the 300na current source is rated at 25c. at -55c, the current source double to approximately 600na. this feature is particularly useful in thermocouple applications when the user wants to drive a suspected open thermocouple lead to a supply rail. 0 normal mode. 1 activate current source. nu (not used) [17:16] [1:0] these bits are reserved for future upgrade. configuration register to ease the architectural design, the configuration register is thirty-two bits long, however, only nine of the thirty two bits are used. the following sec- tions detail the bits in the configuration register. power consumption the cs5531/32/33/34 accommodate four power consumption modes: normal, low power, standby, and sleep. the normal mode, the default mode, is entered after power is applied to the adc and typ- ically consumes tbd mw. the low power mode is an alternate mode that reduces the consumed power to tbd mw. it is entered by setting the lpm (low power mode) bit in the configuration register to logic 1. slightly degraded noise or linearity perfor- mance should be expected in the low power mode. the last two modes are referred to as the power save modes. they power down most of the analog portion of the chip and stop filter convolutions. the power save modes are entered whenever the power down (pdw) bit of the configuration register is set to logic 1. the particular power save mode entered depends on state of the pss (power save select) bit. if pss is logic 0, the converter enters the stand- by mode reducing the power consumption to tbd mw. the standby mode leaves the oscillator and the on-chip bias generator for the analog portion of the chip active. this allows the converter to quickly return to the normal or low power mode once pdw is set back to a logic 1. if pss and pdw are both set to logic 1, the sleep mode is entered reducing the consumed power to around tbd m w. since this sleep mode disables the oscillator, approximately a 20 ms oscillator start-up delay period is required
cs5531/32/33/34 22 ds289pp1 before returning to the normal or low power mode. if an external clock is used no delay is necessary. reset system the reset system (rs) bit permits the user to per- form a system reset. a system reset can be initiated at any time by writing a logic 1 to the rs bit in the configuration register. after a system reset cycle is complete, the reset valid (rv) bit is set indicating that the internal logic was properly reset. the rv bit is cleared after the configuration register is read. note that the on-chip registers are initialized to the following states. further note that after reset the rs bit automatical- ly returns to logic 0 and the adcs return to the command mode where they wait for a valid com- mand. input short the input short bit allows the user to short the in- puts of the instrumentation amplifier together. this is a useful function because it allows the user to easily test the grounded input performance of the adc and eliminate the noise effects due to the ex- ternal system. guard signal the guard signal bit is a bit that modifies the func- tion of a0. when set, this bit outputs the common mode voltage of the instrumentation amplifier on a0. this feature is useful when the user wants to connect an external shield to the common mode po- tential of the instrumentation amplifier to protect against leakage. figure 5 illustrates a typical con- nection diagram for the guard signal. voltage reference select the voltage reference select (vrs) bit selects the size of the sampling capacitor used to sample the voltage reference. the bit should be set based upon the magnitude of the reference voltage to achieve optimal performance. figures 6 and 7 model the ef- fects on the references input impedance and input current for each vrs setting. as the models show, the reference includes a coarse/fine charge buffer which reduces the dynamic current demand of the external reference. configuration register: 00000000(h) offset registers: 00000000(h) gain registers: 08000000(h) channel setup registers: 00000000(h) common mode = 2.5 v out m center out p x1 +5 va + 40 m a typical v + in v - in cs5531/32/33/34 ain+ ain- a0 figure 5. guard signal shielding scheme. vref c = 22pf f = 2 f fine 1 v 15 mv i = fv c os os n f coarse xin 16 vrs = 1; 1 v v 2.5 v ref figure 6. input reference model when vrs = 1. vref c = 11pf f = 2 f fine 1 v 30 mv i = fv c os os n f coarse xin 16 vrs = 0; 2.5 v < v va+ ref figure 7. input reference model when vrs = 0.
cs5531/32/33/34 ds289pp1 23 the references input buffer is designed to accom- modate rail-to-rail (common-mode plus signal) in- put voltages. the differential voltage between the vref+ and vref- can be any voltage from 1.0 v up to va+ (depending on how vrs is configured), however, the vref+ cannot go above va+ and the vref- pin can not go below va-. for a single- ended reference voltage, the reference voltage is in- put into the vref+ pin of the converter and the vref- pin is grounded. note that if 3 v supplies are used, the supplies must be established before the reference voltage. output latch pins the a1-a0 pins of the adcs mimic the d21- d20/d5-d4 bits of the channel-setup registers if the output latch select bit is logic 0 (default). if the output latch select bit is logic 1 then a1-a0 mimic the output latch bit setting in the configuration reg- ister. these two options give the user a choice of al- lowing the latch outputs to change anytime a different csr is selected for a conversion; or to al- low the latch bits to remain latched to a fixed state (determined by the configuration register bit) for all csr selections. in either case, a1-a0 can be used to control external multiplexers and other log- ic functions outside the converter. the a1-a0 out- puts can sink or source at least 1 ma, but it is recommended to limit drive currents to less than 20 m a to reduce self-heating of the chip. these out- puts are powered from va+ and va-. their output voltage will be limited to the va+ voltage for a logic 1 and va- for a logic 0.
cs5531/32/33/34 24 ds289pp1 configuration register descriptions pss (power save select)[31] 0 standby mode (oscillator active, allows quick power-up). 1 sleep mode (oscillator inactive). pdw (power down mode)[30] 0 normal mode 1 activate the power save select mode. rs (reset system)[29] 0 normal operation. 1 activate a reset cycle. bit automatically returns to logic 0 after reset. rv (reset valid)[28] 0 normal operation 1 system got reset. this bit is read only. bit is cleared to logic zero after the configuration register is read. is (input short)[27] 0 normal input 1 all signal input pairs for each channel are shorted internally. gb (guard signal bit)[26] 0 normal operation of a0 as an output latch. 1 a0s output is modified to output the common mode output voltage of the instrumentation amplifier. vrs (voltage reference select)[25] 0 2.5 v < v ref va+ 11 v v ref 2.5v a1-a0 (output latch bits)[24:23] the latch bits (a0 and a1) will be set to the logic state of these bits upon command word execution if the logic select bit (ols) is set. note that these logic outputs are powered from va+ and va-. 00 a0 = 0, a1 = 0 01 a0 = 0, a1 = 1 10 a0 = 1, a1 = 0 11 a0 = 1, a1 = 1 output latch select, ols[22] 0 when low, uses the channel-setup register as the source of a1 and a0. 1 when set, uses the configuration register as the source of a1 and a0. lpm (low power mode)[21] 0 normal mode 1 reduced power mode nu (not used)[20:0] 0 must always be logic 0. reserved for future upgrades. d31(msb) d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 pss pdw rs rv is gb vrs a1 a0 ols lpm nu nu nu nu nu d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 nu nu nu nu nu nu nu nu nu nu nu nu nu nu nu nu
cs5531/32/33/34 ds289pp1 25 calibration calibration is used to set the zero and gain slope of the adcs transfer function. the cs5531/32/33/34 offer both self calibration and system calibration. note: 1) after the adcs are reset, they are functional and can perform measurements without being calibrated (remember that the vrs bit in the configuration register must be configured). in this case, the converter will utilize the initialized values of the on-chip registers (gain = 1.0, offset = 0.0) to calculate output words. any initial offset and gain errors in the internal circuitry of the chip will remain. 2) calibrations steps each take one conversion cycle to complete. at the end of the calibration step, sdo falls low to indicate that a calibration is complete. 3) offset calibration must be performed before gain calibration because the gain slope is referenced from the offset calibrations. calibration registers the cs5531/32/33/34 converters have an individu- al offset and gain register for each channel input. the gain and offset registers, which are used during both self and system calibration, are used to set the zero and gain slope of the converters transfer func- tion. as shown in offset register section, one lsb in the offset register is 2 -24 proportion of the input span (bipolar span is 2 times the unipolar span). the msb in the offset register determines if the offset to be trimmed is positive or negative (0 pos- itive, 1 negative). note that the magnitude of the offset that is trimmed from the input is mapped through the gain register. the converter can typi- cally trim 100 percent of the input span. as shown in the gain register section, the gain register spans from 0 to (32 - 2 -22 ). the decimal equivalent mean- ing of the gain register is where the binary numbers have a value of either zero or one (b d28 corresponds to bit d28). gain register the gain register span is from 0 to (32-2 -24 ). after reset d24 is 1, all other bits are 0. offset register one lsb represents 2 -24 proportion of the input span (bipolar span is 2 times unipolar span). offset and data word bits align by msb. after reset, all bits are 0. db d 28 2 4 b ( d 27 2 3 b d 26 2 2 ? b n 2 n C ) ++++ b d 28 2 4 b i 2 i C i 0 = n ? + == msb d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 nu nu 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 0000000100000000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 22 2 -23 2 -24 0000000000000000 msb d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 sign 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 0000000000000000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 nu nu nu nu nu nu nu nu 0000000000000000
cs5531/32/33/34 26 ds289pp1 performing calibrations to perform a calibration the user must send a com- mand byte with its msb=1, its pointer bits (csrp2-csrp0) set to address the desired setup to calibrate, and the appropriate calibration bits (cc2- cc0) set to choose the type of calibration to be per- formed. note that calibration assumes that the csrs have been previously initialized because the information concerning the physical channel, its filter rate, gain range, and polarity, comes from the channel-setup register being addressed by the pointer bits in the command byte. once the csrs are initialized, a calibration can be performed with one command byte. once a calibration cycle is complete, sdo falls and the results are stored in either the gain or offset reg- ister for the physical channel being calibrated. note that if additional calibrations are performed on the same physical channel referenced by a different setups with different filter rates, gain ranges, or conversion modes, the last calibration results will replace the effects from the previous calibration as only one offset and gain register is available per physical channel. further note that only one cali- bration is performed with each command byte. to calibrate all the channels additional calibration commands are necessary. self calibration the cs5531/32/33/34 offer both self offset and self gain calibrations. for the self-calibration of offset, the converters internally tie the inputs of the ampli- fier together and routes them to the ain- pin as shown in figure 8. for proper self-calibration of offset to occur, the ain pins must be at the proper common-mode-voltage as specified in the analog characteristics section. for self-calibration of gain, the differential inputs of the modulator are connected to vref+ and vref- as shown in figure 9. self-calibration of gain is performed in the gain = 1x mode without regard to the setup registers gain setting. gain er- rors in the pgia gain steps 2x through 32x are not calibrated as this would require an accurate low voltage source other than the reference voltage. a system calibration of gain should be performed if accurate gains are to be achieved on the 2x through 32x ranges. system calibration for the system calibration functions, the user must supply the converters calibration signals which repre- sent ground and full scale. when a system offset cal- ibration is performed, a ground reference signal must be applied to the converters. figure 10 illustrates sys- tem offset calibration. as shown in figure 11, the user must input a signal representing the positive full scale point to perform a system gain calibration. in either case, the cali- bration signals must be within the specified calibra- tion limits for each specific calibration step (refer to the system calibration specifications ). ain+ ain- s1 open s2 closed + - xgain + - figure 8. self calibration of offset. ain+ ain- open + - xgain + - open closed vref+ closed vref- + - reference figure 9. self calibration of gain.
cs5531/32/33/34 ds289pp1 27 calibration tips calibration steps are performed at the output word rate selected by the wr2-wr0 bits of the channel setup registers. since higher word rates result in conversion words with more peak-to-peak noise, calibration should be performed at lower output word rates. also, to minimize digital noise near the device, the user should wait for each calibration step to be completed before reading or writing to the serial port. for maximum accuracy, calibrations should be per- formed for both offset and gain (selected by chang- ing the g2-g0 bits of the channel-setup registers). note that only one gain range can be calibrated per physical channel. and if factory calibration of the users system is performed using the system cali- bration capabilities of the cs5531/32/33/34, the offset and gain register contents can be read by the system microcontroller and recorded in eeprom. these same calibration words can then be uploaded into the offset and gain registers of the converter when power is first applied to the system, or when the gain range is changed. note that if a user wants to use uncalibrated con- versions, the uncalibrated gain accuracy is 1 per- cent. further note that the gain tracking from range to range is not affected by calibration. gain track- ing from range to range is 0.1 percent. limitations in calibration range system calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the analog input section of this data sheet. for gain calibration, the full scale input signal can be reduced to the point in which the gain register reaches its upper limit of (32-2 -64 decimal). under nominal conditions, this occurs with a full scale input signal equal to about 1/32 the nominal full scale. with the converters intrinsic gain error, this full scale input signal may be higher or lower. in defining the minimum full scale calibration range (fscr) under analog characteristics , mar- gin is retained to accommodate the intrinsic gain error. alternatively the input full scale signal can be increased to a point in which the modulator reaches its 1s density limit of 90 percent, which under nominal condition occurs when the full scale input signal is 1.1 times the nominal full scale. with the chips intrinsic gain error, this input full scale input signal maybe higher or lower. in defin- ing the maximum fscr, margin is again incorpo- rated to accommodate the intrinsic gain error. + - xgain + - external connections 0v + - ain+ ain- cm + - figure 10. system calibration of offset. + - xgain + - external connections full scale + - ain+ ain- cm + - figure 11. system calibration of gain.
cs5531/32/33/34 28 ds289pp1 performing conversions the cs5531/32/33/34 offers two modes of per- forming conversions. the three sections that follow detail the differences and provide examples illus- trating how to use the conversion modes with the channel-setup registers. single conversion mode (mc = 0) based on the information provided in the channel- setup registers (csrs), a single conversion is per- formed after the user transmits the single conver- sion command. the command byte includes a pointer address to the setup register to be used dur- ing the conversion. once transmitted, the serial port enters data mode where it waits until a conver- sion is complete. after the conversion is done, sdo falls to logic 0. forty sclks are then needed to read the conversion. the first 8 sclks are used to clear the sdo flag. during the first 8 sclks, sdi must be logic 0. the last 32 sclks are needed to read the conversion result. note that the user is forced to read the conversion in single conversion mode as sdo will remain low (i.e. the serial port is in data mode) until sclk transitions 40 times. af- ter reading the data, the serial port returns to the command mode, where it waits for a new command to be issued. note: in single conversion mode only fully settled data conversions are output to the data conversion register. since the converter uses a sinc 5 filter for the 3840 hz word rate, the effective word rate in the single conversion mode will be 1/5 the normal rate (3840/5 which is 768 hz, xin = 4.9152 mhz). since the converter uses a sinc 3 filter for all other rates, their effective rates will be cut by 1/3 as three conversion are required to fully settle the sinc 3 filter. multiple conversions mode (mc = 1) based on the information provided in the channel- setup registers (csrs), a single conversion is re- peatedly performed using the setup register con- tents pointed to by the conversion command. the command byte includes a pointer address to the setup register to be used during the conversion. once transmitted, the serial port enters data mode where it waits until a conversion is complete. after the conversion is done, sdo falls to logic 0. forty sclks are then needed to read the conversion. the first 8 sclks are used to clear the sdo flag. the last 32 sclks are needed to read the conversion result. if 00000000 is provided to sdi during the first 8 sclks when the sdo flag is cleared, the converter remains in this conversion mode and continues to convert the selected channel using the same csr setup. while in this mode, not every conversion word needs to be read. the user needs only to read the conversion words required for the application as sdo rises and falls to indicate the availability of a new conversion. note that if a con- version is not read it will be lost and replaced by a new conversion. to exit this conversion mode the user must provide 11111111 to the sdi pin dur- ing the first 8 sclks. if the user decides to exit, 32 sclks are required to clock out the last conversion before the converter will return to the command mode. use of pointers in command byte any time a calibration or conversion command is issued (c, mc, and cc2-cc0 bits must be properly set), the csrp2-csrp0 bits in the command byte are used as pointers to address one of the setups in the channel-setup registers (csrs). table 1 details the address decoding of the pointer the bits. (csrp2-csrp0) csr location setup 000 csr #1 1 001 csr #1 2 010 csr #2 3 011 csr #2 4 100 csr #3 5 101 csr #3 6 110 csr#4 7 111 csr #4 8 table 1. command byte pointer table
cs5531/32/33/34 ds289pp1 29 the examples that follow detail situations that a user might encounter when acquiring a conversion or calibrating the converter. these examples as- sume that the csrs are programmed with the fol- lowing physical channel order: 4, 1, 1, 2, 4, 3, 4, 4. a physical channel is defined as the actual input channel (ain1 to ain4) to which an external sig- nal is connected. example 1: single conversion with setup 1. the command issued is 10000000. these settings in- struct the converter to perform a single conversion with setup 1s settings as csrp2 - csrp0 = 000 (which happens to be physical channel 4 in this ex- ample). after the command is received and decod- ed the adc performs a conversion on physical channel 4 and then sdo falls to indicate that the conversion is complete. to read the conversion, 40 sclks are then required. once acquired, the serial port returns to the command mode. example 2: continuous conversion with setup 3. the command issued is 11010000. these settings instruct the converter to perform continuous con- versions with setup 3s settings as csrp2 - csrp0 = 010 (which happens to be physical channel 1 in this example). after the command is received and decoded the adc performs a conversion on physi- cal channel 1 and then sdo falls to indicate that the conversion is complete. the user now has three op- tions. the user can acquire the conversion and re- main in this mode, acquire the conversion and exit this mode, or ignore the conversion and wait for a new conversion at the next update interval. example 3: calibration with setup 4. the command issued is 10011001. these settings instruct the converter to perform a self offset calibration with setup 4s settings as csrp2 - csrp0 = 011 (which happens to be physical channel 2 in this ex- ample). after the command is received and decod- ed the adc performs a self offset calibration on physical channel 2 and then sdo falls to indicate that the calibration is complete. to perform addi- tional calibrations, more commands have to be is- sued. note: the csrs need not be written. if they are not initialized, all the setups point to their default settings irrespective of the single conversion, multiple single conversion, or calibration mode (i.e conversion can be performed, but only physical channel 1 will be converted). further note that filter convolutions are reset (i.e. flushed) if consecutive conversions are performed on two different physical channels. if consecutive conversions are performed on the same physical channel, the filter is not reset. this allows the adcs to more quickly settle full scale step inputs. conversion output coding the cs5531/32/33/34 output 16-bit (cs5531/33) and 24-bit (cs5532/34) data conversion words. to read a conversion word the user must read the con- version data register. the conversion data register is 32 bits long and outputs the conversions msb first. the last byte of the conversion data register contains data monitoring flags. the channel indica- tor (ci) bits keep track of which physical channel was converted and the overrange flag (of) moni- tors to determine if a valid conversion was per- formed. refer to the conversion data register descriptions section for more details. the cs5531/32/33/34 output data conversions in binary format when operating in unipolar mode and in two's complement when operating in bipolar mode. refer to the output coding section for more details.
cs5531/32/33/34 30 ds289pp1 conversion data register descriptions cs5531/33 (16-bit conversions) cs5532/34 (24-bit conversions) conversion data bits [31:16 for cs5531/33; 31:8 for cs5532/34] these bits depict the latest output conversion. nu (not used) [15:3 for cs5531/33; 7:3 for cs5532/34] these bits are masked logic zero. of (over-range flag bit) 0 bit is clear when over-range condition has not occurred (read only). 1 bit is set when input signal is more positive than the positive full scale, more negative than zero (unipolar mode) or when the input is more negative than the negative full scale (bipolar mode). ci (channel indicator bits) [1:0] these bits indicate which physical input channel was converted. 00 physical channel 1 01 physical channel 2 10 physical channel 3 11 physical channel 4 d31(msb) d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 msb14131211109 87654321lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 00000 0 000000ofci1ci0 d31(msb) d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 msb 2221201918 17 16151413121110 9 8 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 7 65432 1lsb00000ofci1ci0
cs5531/32/33/34 ds289pp1 31 output coding digital filter the cs5531/32/33/34 have linear phase digital fil- ters which are programmed to achieve a range of output word rates (owrs) as stated in the channel- setup register descriptions section. the adcs use a sinc 5 digital filter to output word rates at 3840 hz (xin = 4.9152 mhz). other output word rates are achieved by using a sinc 3 filter with a programma- ble decimation (see figure 12). the sinc 3 is active for all output word rates except for the 3840 hz (xin = 4.9152 mhz) rate. the converters digital filters scale with xin. for example, with an output word rate of 120 hz, the filters corner frequency is typically 31 hz. if xin is increased to 5.0 mhz, the owr increases by 1.0175 percent and the filters corner frequency moves to 31.54 hz. note that the converter isnt specified to run at xin clock frequencies greater than 5 mhz. clock generator the cs5531/32/33/34 include an on-chip inverting amplifier which can be connected with an external crystal to provide the master clock for the chip. the chips are designed to operate using a 4.9152 mhz crystal; however, other crystal with frequencies be- tween 1 mhz to 5 mhz can be used. one lead of the crystal should be connected to xin and the oth- er to xout. lead lengths should be minimized to reduce stray capacitance. note that while using the on chip oscillator, xout is not designed to direct- note: vfs in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between full scale for any of the bipolar gain ranges. see text about error flags under overrange conditions. unipolar input voltage offset binary bipolar input voltage two's complement unipolar input voltage offset binary bipolar input voltage two's complement >(vfs-1.5 lsb) ffff >(vfs-1.5 lsb) 7fff >(vfs-1.5 lsb) ffffff >(vfs-1.5 lsb) 7fffff vfs-1.5 lsb ffff ------ fffe vfs-1.5 lsb 7fff ------ 7ffe vfs-1.5 lsb ffffff ------ fffffe vfs-1.5 lsb 7fffff ------ 7ffffe vfs/2-0.5 lsb 8000 ------ 7fff -0.5 lsb 0000 ------ ffff vfs/2-0.5 lsb 800000 ------ 7fffff -0.5 lsb 000000 ------ ffffff +0.5 lsb 0001 ------ 0000 -vfs+0.5 lsb 8001 ------ 8000 +0.5 lsb 000001 ------ 000000 -vfs+0.5 lsb 800001 ------ 800000 <(+0.5 lsb) 0000 <(-vfs+0.5 lsb) 8000 <(+0.5 lsb) 000000 <(-vfs+0.5 lsb) 800000 table 2. output coding for 16-bit cs5531/33 and 24-bit cs5532/34. cs5531/33 16-bit output coding cs5532/34 24-bit output coding figure 12. digital filter response (word rate = 60 hz). frequency (hz) notch depth (db) frequency (hz) minimum attenuation (db) 50 (xin = 4.096mhz) tbd tbd tbd 60 (xin = 4.9152mhz) tbd tbd tbd table 3. filter notch attenuation. -120 -80 -40 0 gain (db) 0 60 120 180 240 300 frequency (hz)
cs5531/32/33/34 32 ds289pp1 ly drive any off chip logic. when the on chip oscil- lator is used, the voltage on xout is typically 1/2 v peak-to-peak. this signal is not compatible with external logic unless additional external circuitry is added. the designer can use an external cmos compati- ble oscillator to drive xin with a 1 mhz to 5 mhz clock for the adc. in this scheme, xout is left unconnected. power supply arrangements the cs5531/32/33/34 are designed to operate from single or dual analog supplies and a single digital supply. the following power supply connections are possible: va+ = +5 v; va- = 0 v; vd+ = +3 v to +5 v va+ = +2.5 v; va- = -2.5 v; vd+ = +3 v to +5 v va+ = +3 v; va- = -3 v; vd+ = +3 v figure 13 illustrates the cs5532 connected with a single +5.0 v supply to measure differential inputs relative to a common mode of 2.5 v. figure 14 il- lustrates the cs5532 connected with 2.5 v bipolar analog supplies and a +3 v to +5 v digital supply to measure ground referenced bipolar signals. fig- ure 15 illustrates the cs5532 connected with 3 v analog supplies and a +3 v digital supply to mea- sure ground referenced bipolar signals. figure 16 illustrates alternate bridge configurations which can be measured with the converter. voltage v1 can be measured with the pgia gain set to 1x as the input amplifier on this gain setting can go rail-to-rail. voltage v2 should be measured with the pgia gain set at 2x or higher as the instrumen- tation amplifier used on these gain ranges achieves lower noise. its input cannot measure rail-to-rail. getting started this part has several features. from a software pro- spective, what should be done first? since no pow- er-on-reset function is provided on the cs5531/32/33/34, the user must first initialize the adc to a known state. this is accomplished by re- setting the adcs serial port with the serial port initialization sequence. this sequence resets the se- rial port to the command mode and is accomplished by transmitting 15 sync1 command bytes (0xff hexadecimal), followed by one sync0 command (0xfe hexadecimal). once the adc is in a known figure 13. cs5532 configured with a single +5 v supply. xout vd+ va+ vref+ vref- dgnd va - ain1+ sdi sclk sdo cs5532 xin cs 10 w +5 v analog supply 0.1 f 0.1 f + - 17 3 1 2 ain1- 515 9 10 13 11 12 14 16 6 optional clock source serial data interface 4.9152 mhz 20 ain2+ 19 ain2- 7 a0 8 a1 c1 c2 4 22 nf 18
cs5531/32/33/34 ds289pp1 33 state (in this case the command mode), the user must reset all the internal logic by performing a system reset. this is accomplished by setting the reset system (rs) bit in the configuration register. after a system reset cycle is complete, the rs bit is automatically returned to logic 0, all on-chip logic is initialized to its proper state, and the adc is re- turned to the command mode where it waits for the next valid command to execute. the next action is to initialize the voltage reference mode. the volt- age reference select (vrs) bit in the configuration register must be set based upon the magnitude of the reference voltage between the vref+ and the vref- pins. after this, initialize the channel-setup registers (csrs) as these registers determine how calibra- tions and conversions will be performed. once the csrs are initialized, the user has three options in calibrating the adc: 1) dont calibrate and use the default settings; 2) perform self or system calibra- tions; or 3) upload previously saved calibration re- sults to the offset and gain registers. once xout vd+ va+ vref+ vref- dgnd va - ain1+ sdi sclk sdo cs5532 xin cs +2.5 v analog supply 0.1 f 0.1 f + - 17 3 1 2 ain1- 515 9 10 13 11 12 14 16 6 optional clock source serial data interface 4.9152 mhz 20 ain2+ 19 ain2- 7 a0 8 a1 c1 c2 4 22 nf -2.5 v analog supply 18 +3 v ~ +5 v digital supply figure 14. cs5532 configured with 2.5 v analog supplies. xout vd+ va+ vref+ vref- dgnd va - ain1+ sdi sclk sdo cs5532 xin cs 10 w +3 v analog supply 0.1 f 0.1 f + - 17 3 1 2 ain1- 515 9 10 13 11 12 14 16 6 optional clock source serial data interface 4.9152 mhz 20 ain2+ 19 ain2- 7 a0 8 a1 c1 c2 4 22 nf -3 v analog supply 18 figure 15. cs5532 configured with 3 v analog supplies.
cs5531/32/33/34 34 ds289pp1 calibrated, the adc is ready to perform conver- sions. pcb layout the cs5531/32/33/34 should be placed entirely over an analog ground plane with both the agnd and dgnd pins of the device connected to the an- alog plane. place the analog-digital plane split im- mediately adjacent to the digital portion of the chip. note: see the cdb5531/32/33/34 data sheet for suggested layout details and applications note 18 for more detailed layout guidelines. before layout, please call for our free schematic review service. v+ v+ v v v v 1 2 1 2 (a) (b) figure 16. bridge with series resistors.
cs5531/32/33/34 ds289pp1 35 pin descriptions clock generator xin; xout - crystal in; crystal out. an inverting amplifier inside the chip is connected between these pins and can be used with a crystal to provide the master clock for the device. alternatively, an external (cmos compatible) clock (powered relative to vd+) can be supplied into the xin pin to provide the master clock for the device. control pins and serial data i/o cs - chip select. when active low, the port will recognize sclk. when high the sdo pin will output a high impedance state. cs should be changed when sclk = 0. 1 2 3 4 5 6 7 817 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 cs5533/4 vref+ vref- cs dgnd sdo serial data input logic output (analog) positive analog power amplifier capacitor connect amplifier capacitor connect differential analog input crystal in chip select voltage reference input voltage reference input differential analog input differential analog input logic output (analog) positive digital power digital ground serial data out crystal out differential analog input ain2+ ain2- sdi vd+ negative analog power differential analog input differential analog input differential analog input differential analog input ain3- ain3+ a1 a0 va- va+ c2 c1 ain1- ain1+ xin xout ain4- ain4+ sclk serial clock input 1 2 3 4 5 6 7 813 14 15 16 17 18 19 20 vref+ vref- sclk cs dgnd a1 a0 va- va+ c2 c1 ain1- ain1+ 9 10 11 12 sdo xin xout serial data input logic output (analog) positive analog power amplifier capacitor connect amplifier capacitor connect differential analog input crystal in chip select voltage reference input voltage reference input differential analog input differential analog input logic output (analog) serial clock input positive digital power digital ground serial data out crystal out cs5531/2 differential analog input ain2+ ain2- sdi vd+ negative analog power
cs5531/32/33/34 36 ds289pp1 sdi - serial data input. sdi is the input pin of the serial input port. data will be input at a rate determined by sclk. sdo - serial data output. sdo is the serial data output. it will output a high impedance state if cs = 1. sclk - serial clock input. a clock signal on this pin determines the input/output rate of the data for the sdi/sdo pins respectively. this input is a schmitt trigger to allow for slow rise time signals. the sclk pin will recognize clocks only when cs is low. a0, a1 - logic outputs (analog). the logic states of a0-a1 mimic the states of the d22/d10-d23/d11 bits of the channel-setup register. logic output 0 = va-, and logic output 1 = va+. measurement and reference inputs ain1+, ain1-, ain2+, ain2- ain3+, ain3-, ain4+, ain4- - differential analog input. differential input pins into the cs5531. vref+, vref- - voltage reference input. fully differential inputs which establish the voltage reference for the on-chip modulator. c1, c2 - amplifier capacitor inputs. connections for the instrumentation amplifiers capacitor. power supply connections va+ - positive analog power. positive analog supply voltage. vd+ - positive digital power. positive digital supply voltage (nominally +3.0 v or +5 v). va- - negative analog power. negative analog supply voltage. dgnd - digital ground. digital ground.
cs5531/32/33/34 ds289pp1 37 specification definitions linearity error the deviation of a code from a straight line which connects the two endpoints of the adc transfer function. one endpoint is located 1/2 lsb below the first code transition and the other endpoint is located 1/2 lsb beyond the code transition to all ones. units in percent of full- scale. differential nonlinearity the deviation of a code's width from the ideal width. units in lsbs. full scale error the deviation of the last code transition from the ideal [{(vref+) - (vref-)} - 3/2 lsb]. units are in lsbs. unipolar offset the deviation of the first code transition from the ideal (1/2 lsb above the voltage on the ain- pin.). when in unipolar mode (u/b bit = 1). units are in lsbs. bipolar offset the deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 lsb below the voltage on the ain- pin). when in bipolar mode (u/b bit = 0). units are in lsbs. ordering guide model number bits channels linearity error (max) temperature range package cs5531-ap 16 2 0.003% -40 c to +85 c 20-pin 0.3" plastic dip cs5531-as 16 2 0.003% -40 c to +85 c 20-pin 0.2" plastic ssop CS5532-BP 24 2 0.0015% -40 c to +85 c 20-pin 0.3" plastic dip cs5532-bs 24 2 0.0015% -40 c to +85 c 20-pin 0.2" plastic ssop cs5533-ap 16 4 0.003% -40 c to +85 c 24-pin 0.3" skinny plastic dip cs5533-as 16 4 0.003% -40 c to +85 c 24-pin 0.2" plastic ssop cs5534-bp 24 4 0.0015% -40 c to +85 c 24-pin 0.3" skinny plastic dip cs5534-bs 24 4 0.0015% -40 c to +85 c 24-pin 0.2" plastic ssop
cs5531/32/33/34 38 ds289pp1 package drawings notes: 1. positional tolerance of leads shall be within 0.25 mm (0.010 in.) at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 3. dimension e does not include mold flash. inches millimeters dim min max min max a 0.155 0.180 3.94 4.57 a1 0.020 0.040 0.51 1.02 b 0.015 0.022 0.38 0.56 b1 0.050 0.065 1.27 1.65 c 0.008 0.015 0.20 0.38 d 0.960 1.040 24.38 26.42 e 0.240 0.260 6.10 6.60 e 0.095 0.105 2.41 2.67 ea 0.300 0.325 7.62 8.25 l 0.125 0.150 3.18 3.81 0 15 0 15 20 pin plastic (pdip) package drawing e d seating plane b1 e b a l a1 top view bottom view side view 1 ea c
cs5531/32/33/34 ds289pp1 39 notes: 1. positional tolerance of leads shall be within 0.25 mm (0.010 in.) at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 3. dimension e does not include mold flash. inches millimeters dim min max min max a 0.155 0.180 3.94 4.57 a1 0.020 0.040 0.51 1.02 b 0.014 0.022 0.36 0.56 b1 0.040 0.065 1.02 1.65 c 0.008 0.015 0.20 0.38 d 1.235 1.265 31.37 32.13 e 0.240 0.260 6.10 6.60 e 0.095 0.105 2.41 2.67 ea 0.300 0.325 7.62 8.25 l 0.125 0.150 3.18 3.81 0 15 0 15 24 pin skinny (pdip) package drawing e d seating plane b1 e b a l a1 top view bottom view side view 1 ea c
cs5531/32/33/34 40 ds289pp1 notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min max min max a -- 0.084 -- 2.13 a1 0.002 0.010 0.05 0.25 a2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 d 0.272 0.295 6.90 7.50 1 e 0.291 0.323 7.40 8.20 e1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 l 0.025 0.040 0.63 1.03 0 8 0 8 20 pin ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5531/32/33/34 ds289pp1 41 notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min max min max a -- 0.084 -- 2.13 a1 0.002 0.010 0.05 0.25 a2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 d 0.311 0.335 7.90 8.50 1 e 0.291 0.323 7.40 8.20 e1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 l 0.025 0.040 0.63 1.03 0 8 0 8 24 pin ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view

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